I. Field of the Disclosure
The technology of the disclosure relates generally to power control and more particularly to power control in a three-dimensional (3D) integrated circuit (IC) (3DIC).
II. Background
Computing devices have become common in modern society. The rise in numbers of computing devices is due, in part, to the advent of truly portable or mobile computing devices. While such mobile computing devices began as relatively cumbersome and bulky devices that exhausted batteries relatively quickly, increased miniaturization and power saving techniques have made current devices into powerful multimedia devices with extensive functions and generally adequate battery life.
While there has been a recent trend to increase the size of some of the mobile computing devices, especially in the smart phone and tablet categories, such size increases are accompanied by expectations of increased computing power and better battery life. Accordingly, there continues to be pressure to miniaturize the circuitry within the mobile computing devices. Two-dimensional (2D) integrated circuits (ICs) (2DICs) are approaching what seem to be hard physical limits in terms of material behavior as well as limits in manufacturing processes which preclude further miniaturization. The pressure to miniaturize continues unabated in view of these limits. Accordingly, circuit designers have embraced three-dimensional (3D) ICs (3DICs).
While IC manufacturing is a relatively mature industry, such manufacturing processes do not guarantee that semiconductor materials made according to the same process have precisely the same characteristics. That is, most semiconductor materials may experience process variations during the manufacturing processes. Such process variations may result in a semiconductor material that is typical (T), fast (F), or slow (S). Such variations may be different for different types of elements within a single semiconductor material. For example, an N-type Metal Oxide Semiconductor (MOS) (NMOS) field effect transistor (FET) might be fast while a P-type MOS (PMOS) FET might be slow. In the 2D context, variations between devices on a single IC are relatively uniform, and various compensation schemes (typically changing the supply voltage) for the 2DIC have been proposed. However, in a 3DIC context, different tiers of the 3DIC may have different process variations. Having different compensation requirements for different tiers imposes additional power control burdens on circuit designers, including voltage step-ups or voltage step-downs or the like. In some instances, the additional power control burdens make certain tiers unusable in certain 3DIC architectures. Such unusable tiers may be discarded, which increases manufacturing costs. Accordingly, designers would appreciate more options for power control in a 3DIC to compensate for process variations.